This invention relates generally to integrated circuits and more particularly to a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge.
Modern integrated circuits, particularly metal oxide semiconductor (MOS) integrated circuits, commonly employ protection circuits at the input and/or output paths to prevent damage to the integrated circuit caused by electrostatic discharge. As devices are made smaller, they become more sensitive to high voltage electrostatic discharge. During installation of integrated circuits, electrostatic discharge may destroy integrated circuits and may require expensive and tedious repairs on fully manufactured devices which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge on the integrated circuit itself. MOS devices are particularly sensitive as high voltage electrostatic discharge may easily destroy the very thin gate oxides and short channel devices of the integrated circuit.
One commonly used circuit for electrostatic discharge protection is an N-channel MOSFET with the drain electrically connected to an integrated circuit bond pad, its source grounded and its gate connected to ground through a resistive load. Unfortunately, the breakdown voltage of commonly used NMOS transistors may limit the use of this type of circuit for certain applications. One application where use of a single NMOS transistor is problematic is protection for the programming pin in an EPROM type device. The programming voltage ordinarily exceeds the voltage of other signals used to control the EPROM. In addition, the programming voltage may typically be higher than the breakdown voltage of MOS transistors ordinarily used for electrostatic discharge protection. Use of a single MOSFET for electrostatic discharge protection on an EPROM programming pin, then, may interfere with the proper programming of the device.
Field oxide protection devices may be used but are ineffective for more advanced technologies. In some cases, the cycling of the VPP Voltage builds up to result in electrical overstress (EOS) damage on the protection device. Therefore, a sufficient margin between the protection device turn on and the VPP program pin voltage swings is needed.
The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry comprising an integrated circuit with at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.
The invention has several important technical advantages. The invention provides an efficient, easy to use circuit to protect high voltage circuitry electrically connected to a bond pad of an integrated circuit. For example, the invention may be used to protect circuitry connected to input and output pins of an integrated circuit. One example where the invention is particularly useful is the programming pin of an EPROM. The term, xe2x80x9cpin,xe2x80x9d is used broadly and is meant to refer to any conductor connected in some way to a bond pad of an integrated circuit. Thus, the invention may be used for electrostatic discharge protection in integrated circuits having any type of packaging. Because the invention employs two MOSFETs for electrostatic discharge protection, it may be manufactured while the remainder of the protected integrated circuit is manufactured using conventional processes. The invention may also be used as an efficient output protection scheme for floating substrate and non-epi substrate technologies. In addition, the invention may be used to provide further protection to MOSFETs in the integrated circuit by creating a substrate bias.